The invention relates to microprogrammed data processing systems, and particularly to a processor suitable for servicing a plurality of peripheral machines on a preassigned priority basis.
The capacity required of buffering facilities for at least the fastest of the peripheral machines associated with a processing system can be reduced by assigning priorities to the peripheral machines and allowing higher priority machines to interrupt lower priority ones. The facility for handling interrupts may require the processing of microprogram routines of varying complexity and will generally take up considerable processor time, especially for dumping and recovering microcode and data for the interrupt machine, leaving a still significant buffering requirement.
An object of the present invention is to provide a data processing system with an improved facility for handling peripheral interrupts. This is achieved by providing a number of microprogram levels, each level having its own microprogram address register so that changes in microprogram level can be made without the necessity for dumping and undumping the contents of the address registers. Different peripherals are allocated different microprogram levels, so that they can readily interrupt each other. (Additionally, some peripherals may share the same level, but these peripherals will not be able to interrupt each other without dumping the address register).
A processor embodying the invention will generally have its highest priority microprogram level reserved for critical interrupts, e.g. from parity failures or hardware malfunctions. The normal interrupt hierarchy for microprogram levels will thus start with the critical interrupt level and be followed by the peripheral machine related levels with processor-related activity lower still in the hierarchy.
As indicated above, processor activity unrelated to peripheral machine requirements is given the lowest priority and this is interrupted by any peripheral machine request for service. Rather than allocate only one microprogram level to such processor related activity, it is preferred to use a number of levels also arranged hierarchically with each level having its own microprogram address register.
Such provision of a number of processor related microprogram levels with the appropriate registers is preferably associated with a reversible counter for level change control and allows a stacking feature in which nesting of microprogram jumps is managed by incrementing the contents of the microprogram address register for the current level prior to operating the counter to select the next higher priority microprogram level address register for receiving the jump destination. On successful return from a jump, the counter is sequenced to the next lower priority microprogram level.
A convenient total number of microprogram levels is sixteen with eight allocated to processor activity unrelated to peripheral machines, seven higher levels allocated to peripheral related processor activity, and the highest level reserved for critical interrupts. This means that the microprogram address registers will be replicated to a depth of sixteen as will some of the working registers, the remainder of which being held nine deep.
It is preferred for each set of registers to be embodied as a random access word organised memory and for all such memories to be addressable by an indication of the desired microprogram level which will be determined in part by a priority network for assessing the priorities of peripheral machines that request processor time. As has been indicated above such a priority network may be backed by a further one that is effective to select between peripheral machines that share the same microprogram level.
In a preferred embodiment, applications of the level determining indication to the various sets of memories constituting replicated registers is not done simultaneously as the processor operations are overlapped or pipelined with microinstruction fetching, microinstruction decoding, and consequent data flow control for instruction executive taking place in consecutive processor cycles. This means that at any one time, fetching, decoding and execution relative to different microinstructions may be taking place. Appropriate timing of microprogram level changing and register switching is thus required to allow instructions already being serviced to run on to the execution stage.
Preferably, a nullify facility is provided which is operative during such run-on of the pipeline to count from initiations of jump operations or store accesses, so that returns to the interrupted level can be made to a microprogram address modified to point to an instruction corresponding to the initiation of the jump operation. It is preferred that a minimum number of microinstructions be performed before one peripheral level is substituted by another even if of higher priority.
Preferably, the processor is consolidated with standard peripheral facilities in a unitary design in which versatility is provided by specific purpose-designed couplers for each peripheral concerned. These standard facilities each conveniently include far less hardware logic than a normal free standing peripheral machine and, instead, use the microprogram controlled processor to perform necessary control procedures by requests via the coupler concerned. A preferred normal package of peripheral facilities comprises a disc store, card reader, line printer and a video console. A coupler will also be available for direct data entry for which a microprogram store extension may be required. Furthermore, in view of the flexibility of the microprogram control, couplers are readily provided to simulate standard interfaces for other peripheral machines, said to give complete compatibility, so-called "plug-compatibility" with other ranges of machines.
In a preferred implementation, programs of microinstructions can be viewed as comprising two types both of which use a basic set of functions for the arithmetic unit, one being to handle peripheral input/output and controls and the other of which is concerned with implementating a particular target, program function set, such as that developed for a specific computer or range of computer. Preferably, the microprogram store is writable and this gives inherently greater flexibility to the system, particularly in imitating other "target" systems.
It is advantageous to embody the invention using random access writable storage for the microprogram. This will allow replacement of microprogram directed to one target code by microprogram directed to any other target code. Certain features, particularly loading of microprogram and data storage, will be unaffected by target code and it is preferred to store such microprogram material in random access read only storage which, ideally, uses the same constructional technology thereby giving at least compatible cycle times.
For any particular target code it is feasible to use permanently configured storage, e.g. random access read only memory similar to that mentioned above for store loading. Then there will be different storage units for each target code. It is, of course, equally possible to use so-called "hard-wired logic" to decode target code and such an implementation may well use medium or large scale integrated circuits.